As is well known, trench technology is used for isolation of semiconductor devices in an integrated circuit. Examples there of are shown in FIGS. 1A and 1B, indicating use of refilled trenches in CMOS and bipolar technologies.
Typically, common materials used for trench fill are CVD-deposited oxide, nitride, doped or undoped polysilicon or selectively-grown single crystal silicon.
FIG. 2 shows a sequence of steps in the prior art for providing such refilled trench structure, for example, for intra-well isolation of CMOS devices. Such a method is generally disclosed in "Shallow Trench Isolation", P. Krusius, NSC Presentation Notes, 21 pages (1992). For simplicity, only trenches in P well are described. For trenches in N well it will be understood that opposite polarity dopants are used, but that the same principles apply.
As shown in FIG. 2A, silicon substrate 20 has a P-well 22, with successive oxide 24, nitride 26 and oxide 28 (ONO) layers thereon, which are appropriately etched to provide an opening therethrough to the top surface of the substrate 20. A reactive ion etch (RIE) is undertaken to form the trench 30 (in CMOS technology generally less then 0.5 .mu.m deep). An oxidation step is then undertaken to grow oxide 32 on the sidewalls and bottom of the trench 30, for example to the thickness of 70 to 100 nm (FIG. 2B). A further RIE is undertaken to remove the oxide from the bottom of the trench 30 (FIG. 2C). P+ doped polysilicon 34 is then deposited over the resulting structure, filling the trench 30, and subsequently a planarizing layer such as photoresist or SOG 36 is deposited (FIG. 2D). The SOG layer 36 and P+ doped polysilicon 34 are then etched back (FIG. 2E) to leave P+ doped polysilicon 34A in the trench, and a heating step is undertaken to grow cap oxidation 38 to the thickness of for example 100 to 200 nm, and also to form P+ diffusion layer 40 to suppress vertical parasitic conduction. Subsequently, the layers 28, 26 are removed by etching. Thereafter conventional CMOS process flow continues.
Another example of forming a trench in a CMOS device is shown in FIG. 3. Such a method is generally disclosed in "Trench Isolation Prospects for Application in CMOS VLSI", R. D. Rung, IEDM Digest, pp. 574-577 (1984). In this case, the steps of FIGS. 3A and 3B are identical to those of FIGS. 2A and 2B, but then the oxide layer on the bottom of the trench 130 is not removed (FIG. 3C). Subsequent thereto, the trench sidewalls and bottom are implanted with P type dopant to prevent parasitic field and sidewall transistor turn on. Then, for example, undoped polysilicon and/or CVD deposited oxide and/or nitride 150 are deposited in and over the trench 130.
Any common planarization technique, such as CMP, SOG layer 152 or resist deposition (FIG. 3D) and etch back can be undertaken, and conventional CMOS process flow continues (FIG. 3E).
A significant problem with these refill processes is that voids can form in the trench. In addition, the material in the trench may be structurally deficient. The presence of voids and loose structure have a tendency to magnify the formation of defects in active areas during subsequent processing.
With reference to FIG. 4, in bipolar devices, the isolation requires deeper trenches than those necessary in CMOS. For example, trench depths of 2 to 7 microns are typical for bipolar applications. Again, these trenches can be refilled using the techniques previously described in relation to FIGS. 2 and 3 (with or without removing the oxide at the bottom of the trench) and depositing insulating material and undertaking subsequent planarization steps. However, in such a situation, the disadvantages pointed out above of having voids and loosely packed material in the trench are magnified for bipolar applications due to the increased depth of the trench.
FIG. 4 shows a trench-refill technique using selective-epitaxial growth. In this regard, reference is made to U.S. Pat. No. 4,473,598, "Method of Filling Trenches With Silicon and Structures", L. M. Ephrath, V. J. Silvestri and D. D. Tang, issued Sep. 25, 1984; U.S. Pat. No. 4,526,631, "Method for Forming a Void Free Isolation Pattern Utilizing Etch and Refill Techniques", V. Silvestri and D. D. Tang, issued Jul. 2, 1985; "Selective Epitaxial Trench (SET)", V. J. Silvestri, Journal Electrochem. Soc. Vol. 135, pp. 1808-1812 (July 1988); "Trench Isolation by Selective Epi and CVD Oxide Cap", K. D. Beyer, V. J. Silverstri, J. S. Makris, and W. Guthrie, Journal Electrochem. Soc. Vol. 137, pp. 3951-3953 (December 1990); and "A New Trench Isolation Technology As A Replacement of Locos", H. Mikoshiba, T. Homma and K. Hamano, IEDM, pp. 578-581 (1984).
Initially, for example (FIG. 4A), a P- substrate 200 is provided, with N+ and N- layers 202, 204 thereon, and further with an oxide or nitride insulating layer 206 thereover. The insulating layer 206 has an opening therethrough through which the trench RIE is undertaken to form trench 208, down into the P- region 200. Subsequently (FIG. 4B), trench sidewall and bottom wall oxidation is undertaken to from oxide layer 210, and another dielectric layer 212 (for example nitride) is deposited over the resulting structure. An RIE of the bottom composite layer in the trench 208 is undertaken (FIG. 4C), exposing the substrate 200 in the trench 208. Suitable precleaning of the trench 208 is performed, and (FIG. 4D) silicon 214 of appropriate conductivity type is selectively grown in the trench 208, meanwhile forming the diffusion layer 216 for the suppression of parasitic conduction. The selective-growth process is terminated when epitaxial silicon reaches approximately two-thirds of the trench depth.
The process continues with the deposition of oxide, nitride or a combination of these materials 218. Any common planarization technique (FIG. 4E) such as CMP, SOG or resist deposition and etch back completes the trench-refill process.
Although this approach has been found to produce a void-free structure, sharp facets form near the sidewalls of the trench. This facet formation is a very strong function of the cleaning process used before selective epitaxial growth. Furthermore, the temperature of the selective growth process in this embodiment is between 850.degree. C. and 1150.degree. C., which adds considerably to the thermal budget of the process. Additionally, the requirement of filling the top portion of the trench with another insulator, in some cases with multiple layers, adds to the complexity of the process and does not offer any advantages in terms of defect density.